1. Field
This disclosure relates generally to dynamic logic circuits, and more specifically, to dynamic logic circuits with a keeper transistor.
2. Related Art
Dynamic logic circuits are typically used in applications requiring high speed operation. Dynamic logic circuits operate in accordance with a clock signal, in which, during a precharge phase of a clock cycle, the dynamic node of the dynamic logic circuit is precharged to a logic level high, and during a subsequent evaluate phase of the clock cycle, the dynamic logic circuit evaluates the logic inputs. As a result of the evaluation, the dynamic node may maintain the logic level high or be pulled down to a logic level low. A PMOS keeper circuit connected to the dynamic node of the dynamic logic circuit may be used to ensure that the dynamic node is never left floating. For example, during the evaluate phase of the clock, the keeper circuit ensures that the dynamic node does not float by feeding back an output signal of the dynamic logic circuit. However, if, during the evaluate phase of the clock, the inputs of the dynamic logic circuit cause the state of the dynamic node to be pulled low, the keeper circuit must be overcome in order to provide the correct output.